KEY RESPONSIBILITIES
• Good knowledge of front-end design construction and verification.
• Experience in SoC Build, infrastructure tools & debugging integration issues
o Knowledge of AMD flow and infrastructure. Familiarity with DJ
• Expertise in SoC/IP register methodology and & hands-on in IP-SoC integration, related issues & debugging failures
• A working knowledge of IP-XACT focused on interfaces and register descriptions.
• Hands on knowledge and experience with C, C++, Perl, Python, Ruby, TCL, and any other scripting languages
• Familiarity with design Infrastructure such as lsf, parallelism.
• Familiarity with Verilog, SV and Testbench languages.
Work Experience
PRIOR EXPERIENCE
3-5 years of Experience with EDA software development or support, ability to architect solutions to deep problems in front end design construction and verification and implementing infra are a must. Key items of interest are
• Excellent communication and writing skills
• Project execution.
• Customer and partner relations.
• Proposals and strong new initiatives impacting DV methodology