Assist in Design for Testability (DFT) activities for VLSI chip designs.
Support scan insertion, ATPG pattern generation, and simulation tasks.
Work with senior engineers to validate test coverage and resolve issues.
Learn and apply industry-standard DFT tools and methodologies.
Prepare basic documentation and status reports as required.
Bachelor’s degree in Electronics, Electrical, or related field.
Basic understanding of digital design and DFT concepts.
Familiarity with Verilog or VHDL is an advantage.
Good analytical and communication skills
Work Experience
Assist in Design for Testability (DFT) activities for VLSI chip designs.
Support scan insertion, ATPG pattern generation, and simulation tasks.
Work with senior engineers to validate test coverage and resolve issues.
Learn and apply industry-standard DFT tools and methodologies.