Trainee Engineer
QuEST Global
Job Requirements
Knowledgeable in all aspects of deep ASIC design flow.Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.Experience in modifying STA constraints to check timing closure feasibilityKnowledge in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nmGood Communication and interpersonal skills
Work Experience
Knowledgeable in all aspects of deep ASIC design flow.Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.Experience in modifying STA constraints to check timing closure feasibilityKnowledge in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nmGood Communication and interpersonal skills
Knowledgeable in all aspects of deep ASIC design flow.Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.Experience in modifying STA constraints to check timing closure feasibilityKnowledge in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nmGood Communication and interpersonal skills
Work Experience
Knowledgeable in all aspects of deep ASIC design flow.Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.Experience in modifying STA constraints to check timing closure feasibilityKnowledge in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nmGood Communication and interpersonal skills
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