TOP Implementation Engineer
Cisco Systems
MEET THE TEAM
Join Cisco's CHG Team in Armenia, a leader in the physical design and implementation of pioneering networking chips under the globally recognized Silicon One brand. Our team is dedicated to comprehensive chip-level planning and implementation, including floorplanning, chip-level clock structures, through-planning, routing, signoff, and tape-out. We collaborate closely with block implementation teams, top-level signoff teams such as STA, EMIR, and PV, RTL design teams, package teams, IP vendors, tool vendors, and foundries. As part of this forward-thinking and innovative team, you will help ensure the reliability, performance, and quality of the silicon that powers the future of connectivity. Together, we are redefining what's possible in networking technology.
YOUR IMPACT
In this role, you’ll be instrumental in Cisco’s Silicon One development, driving the physical design of next-generation networking chips. Your responsibilities will span the full-chip design process, from die-size estimation and floorplanning to DRC/LVS/ANT checks, ensuring flawless execution and signoff. You’ll partner with diverse teams across the organization, including block-level design, packaging, IP vendors, and foundries, to resolve challenges and optimize implementations. Beyond technical contributions, you’ll join a team that values collaboration, mentorship, and innovation, creating an environment where your growth and success are celebrated.
WHAT YOU'LL DOConduct full-chip physical design activities, including die-size estimation, floorplanning, and routing.Perform DRC, LVS, and ANT checks, debug issues, provide solutions, and ensure signoff cleanliness.Provide critical inputs to block owners, such as block shapes, pin locations, and IP placements.Collaborate with block-level physical design teams to understand implementation challenges and ensure design alignment.Partner closely with the packaging team to implement the chip bump map effectively.Work with IP vendors to ensure correct physical implementation of external IPs.
MINIMUM QUALIFICATIONS3+ years of experience in top-level physical design, including debugging and resolving issues.Strong expertise in deep submicron CMOS technologies and relevant processes.Proven understanding of the CMOS digital design flow and its applications.Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.Excellent verbal and written communication skills in English.
PREFERRED QUALIFICATIONSExperience in physical verification techniques, including DRC, LVS, and EM/IR analysis.Comprehensive knowledge of the full physical design cycle from RTL to GDSII.First-hand experience in ASIC implementation and verification.Proficiency in scripting languages such as Python, Tcl, or Shell to enhance design efficiency.
#WEARECISCO
#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.
Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.
We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do!
Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!
#LI-DTS90
Join Cisco's CHG Team in Armenia, a leader in the physical design and implementation of pioneering networking chips under the globally recognized Silicon One brand. Our team is dedicated to comprehensive chip-level planning and implementation, including floorplanning, chip-level clock structures, through-planning, routing, signoff, and tape-out. We collaborate closely with block implementation teams, top-level signoff teams such as STA, EMIR, and PV, RTL design teams, package teams, IP vendors, tool vendors, and foundries. As part of this forward-thinking and innovative team, you will help ensure the reliability, performance, and quality of the silicon that powers the future of connectivity. Together, we are redefining what's possible in networking technology.
YOUR IMPACT
In this role, you’ll be instrumental in Cisco’s Silicon One development, driving the physical design of next-generation networking chips. Your responsibilities will span the full-chip design process, from die-size estimation and floorplanning to DRC/LVS/ANT checks, ensuring flawless execution and signoff. You’ll partner with diverse teams across the organization, including block-level design, packaging, IP vendors, and foundries, to resolve challenges and optimize implementations. Beyond technical contributions, you’ll join a team that values collaboration, mentorship, and innovation, creating an environment where your growth and success are celebrated.
WHAT YOU'LL DOConduct full-chip physical design activities, including die-size estimation, floorplanning, and routing.Perform DRC, LVS, and ANT checks, debug issues, provide solutions, and ensure signoff cleanliness.Provide critical inputs to block owners, such as block shapes, pin locations, and IP placements.Collaborate with block-level physical design teams to understand implementation challenges and ensure design alignment.Partner closely with the packaging team to implement the chip bump map effectively.Work with IP vendors to ensure correct physical implementation of external IPs.
MINIMUM QUALIFICATIONS3+ years of experience in top-level physical design, including debugging and resolving issues.Strong expertise in deep submicron CMOS technologies and relevant processes.Proven understanding of the CMOS digital design flow and its applications.Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.Excellent verbal and written communication skills in English.
PREFERRED QUALIFICATIONSExperience in physical verification techniques, including DRC, LVS, and EM/IR analysis.Comprehensive knowledge of the full physical design cycle from RTL to GDSII.First-hand experience in ASIC implementation and verification.Proficiency in scripting languages such as Python, Tcl, or Shell to enhance design efficiency.
#WEARECISCO
#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.
Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.
We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do!
Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!
#LI-DTS90
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