Job Requirements
Responsible for all front-end integration activities like Lint, CDC, Synthesis, LEC, Low Power and UPF, formal verification, STA and ECO implementationDo Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve themDo Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failuresDevelop Timing Constraints for RTL-Synthesis and STA-Signoff for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocksImplement, enhance and maintain Synthesis, STA scripts and various automation flowsWork closely with logic design and PnR engineers on logic, timing, power and physical issues
 

Work Experience
Familiarity of ASIC design flow (Front-End, DFT, PnR)Hands on experiences in front-end implementation tasks such as synthesis, constraint developing, timing, area/power analysis, linting, and logic equivalence checksHands on experiences in EDA implementation tools for logic synthesis (DC/FC, Genus), RTL/Netlist Check (SpyGlass Lint), LEC (Formality, Conformal), Multi Voltage Verification (VC LP, Conformal LP), STA (PrimeTime, Tempus)Experiences in multi-clock and multi-power domain designsScripting and programming experience using Perl/Python, TCL, etc.Knowledge of RTL coding using Verilog/System Verilog or Physical Design is a plus