About SiTime

 

SiTime Corporation is the precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power and better reliability. With more than 3 billion devices shipped, SiTime is changing the timing industry. For more information, visit www.sitime.com.

 

Job Summary

 

As a Senor Verification Engineer, you will be part of a team developing MEMS timing ICs. It is not necessary to meet all job requirements to be a qualified candidate for the position. 

 

Responsibilities:

 

Developing SV-RNM models for both analog and mixed-signal circuits  Developing verification plan from chip or block specifications  Developing UVM-based verification environment (scoreboards, monitors, sequencers, etc.)Developing digital-top verification in System Verilog  Defining and writing System Verilog Assertions (SVA) Defining and writing functional coverages and covergroupsRunning simulations and debugging simulation results Reviewing verification results for Tape-out sign-off   Communicating with stakeholders (design/test/verification) to facilitate teamwork and efficientsharing of information and exchange of ideas. 

 

 Minimum Requirements: 

MS (BS) degree in electrical/computer engineering or related fields with 5 (8) years of workexperience doing verification in the semiconductor industry  Good verbal and written communication skills in EnglishProficient in SystemVerilog and SystemVerilog OOPFluency in utilizing scripting languages such as Perl / PythonProficient (through work experience) in verification using UVMStrong experience writing SystemVerilog Assertions (SVA)Understanding of Analog schematic and experience with Cadence Virtuoso Basic understanding of digital design using VerilogAbility to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers Ability to work independently and drive solutions to challenging problems 

 

Desired Qualification: 

 

Experience with generating functional modes for analog blocks using SystemVerilog RNM,Wreal (V-AMS), or similar techniques   Experience with UVM-AMS methodologySolid experience with Formal Property Verification (FPV)Programming experience writing OOP code in C++  Excellent written and verbal communication skills in English Experience with performing analog mixed-signal verificationProven track record in working well with others in fast-paced and collaborative workenvironmentKnowledge of analog designKnowledge of synthesizable digital design Experience working on verification of datapath designs including filters

 

The actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

 

SiTime compensation packages includes base salary, bonus based on achieving your innovation goals and equity. 

 

SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.