Job Requirements
5+ years’ experience with Bachelor’s degree in Electronics Engineering or equivalentKnowledgeable in all aspects of deep submicron ASIC design flow.Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages.Experience in developing PD metrics dashboard scripts for QOR tracking is a plus   Experience in modifying STA constraints to check timing closure feasibilityExperience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targetsExperience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm

Work Experience
5+ years’ experience with Bachelor’s degree in Electronics Engineering or equivalentKnowledgeable in all aspects of deep submicron ASIC design flow.Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages.Experience in developing PD metrics dashboard scripts for QOR tracking is a plus   Experience in modifying STA constraints to check timing closure feasibilityExperience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targetsExperience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm