Develop and execute verification plans for SoC-level designs.
Build UVM/SystemVerilog-based testbenches integrating multiple IPs.
Write and maintain testcases, sequences, assertions, and coverage models.
Perform functional, system, and performance verification.
Debug simulation failures and collaborate closely with designers and architects.
Drive coverage closure and track verification metrics.
Support emulation and FPGA prototyping environments as needed.
Mentor junior engineers and contribute to process improvements.
Required Skills
Strong experience in SystemVerilog and UVM methodology.
Good understanding of SoC architectures, interconnects (AXI, AHB), and protocols.
Hands-on expertise in random constrained stimulus generation and functional coverage.
Proficiency in debug tools (SimVision, Verdi, DVE).
Experience with simulation tools (VCS, Questa, Incisive).
Exposure to gate-level simulations, power-aware verification, and low-power design concepts.
Knowledge of scripting (Perl, Python, Tcl).
Good to Have
Experience in emulation platforms (Palladium, Veloce).
Familiarity with formal verification techniques.
Knowledge of cache coherency protocols and memory subsystems
Education
B.E/B.Tech or M.E/M.Tech in Electronics, related field.
Work Experience
Required Skills
Strong experience in SystemVerilog and UVM methodology.
Good understanding of SoC architectures, interconnects (AXI, AHB), and protocols.
Hands-on expertise in random constrained stimulus generation and functional coverage.
Proficiency in debug tools (SimVision, Verdi, DVE).
Experience with simulation tools (VCS, Questa, Incisive).
Exposure to gate-level simulations, power-aware verification, and low-power design concepts.
Knowledge of scripting (Perl, Python, Tcl).