Define and implement DFT architecture and strategy for complex SoCs and ASICs
Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures
Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows
Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met
Debug DFT-related issues during simulation, emulation, and silicon bring-up
Perform timing analysis and constraints development for DFT logic
Drive silicon validation and yield improvement initiatives related to DFT
Document DFT design and verification methodology
Bachelor’s or Master’s degree in Electronics
4–8 years of hands-on experience in VLSI DFT
Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation
Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.)
Good understanding of RTL design, synthesis, and timing closure
Experience with silicon bring-up and production test support
Excellent problem-solving and debugging skills
Strong communication and teamwork abilities
Experience in low-power DFT techniques
Familiarity with scripting (Perl, Python, Tcl) for automation
Work Experience
Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation
Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.)
Experience in low-power DFT techniques
Familiarity with scripting (Perl, Python, Tcl) for automation
Good understanding of RTL design, synthesis, and timing closure