Client Job Title: RANS SoC Integration Lead Engineer
UST Job Title: Lead II - Semiconductor Product Validation
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The Opportunity:
UST is looking for a highly experienced SoC Integration Lead Engineer to support complex Radio Access Network Software (RANS) solutions. The ideal candidate will lead system-level integration of SoC components, collaborating with architecture, design, and validation teams to drive successful silicon execution and pre/post-silicon validation
Key Roles & Responsibilities:
· Lead the integration of multiple IPs into SoC subsystems for wireless communication platforms
· Define and manage integration plans, milestone schedules, and delivery checkpoints
· Collaborate with RTL, physical design, DFT, and verification teams to align integration requirements Debug and resolve SoC-level functional issues and interoperability problems
· Coordinate cross-functional teams to validate SoC architecture, data path, and control logic
· Work with post-silicon teams to drive bring-up, validation, and performance tuning
· Ensure delivery of clean RTL drops and full package signoff for downstream flows
· Develop integration testbenches and execute sanity and regression testing
· Interface with firmware and system software teams to support hardware-software co-design
· Mentor junior engineers and drive integration best practices across programs
Required Skills:
· 14+ years of experience in SoC development and IP/subsystem integration
· Deep understanding of RTL design, interconnect protocols (AMBA, AXI, AHB), and SoC architecture
· Proven experience in resolving integration issues related to clocks, resets, power domains, and bus protocols
· Strong background in synthesis, STA, DFT, and low power flows
· Expertise in using tools like SpyGlass, Verdi, VCS/Questa, and waveform analysis
· Experience with scripting (TCL, Python, Perl) to automate integration flows
· Familiarity with wireless modem/RAN architecture is a strong plus
Desired Skills:
· Experience with pre-silicon emulation, prototyping, or FPGA-based SoC validation
· Working knowledge of system-level modeling and simulation (SystemC, TLM)
· Exposure to firmware development, SoC bring-up, and post-silicon validation workflows
· Familiarity with Git, Jira, Confluence, and CI/CD automation tools
Qualification:
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
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