Company:Qualcomm Semiconductor Limited

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:

​We are looking for a highly analytical and detail-oriented engineer to join our team as a PMIC Yield Diagnostics Engineer. In this role, you will be responsible for managing, analyzing, and improving the yield performance of Power Management IC (PMIC) products. The ideal candidate will have a strong academic background (M.S. or Ph.D.) and hands-on experience in semiconductor yield & diagnostics engineering, with a solid understanding of high-voltage (HV) devices and BCD (Bipolar-CMOS-DMOS) process technologies. You will work closely with cross-functional teams including process, test, and quality engineering to identify yield detractors and drive continuous improvement.

Key Responsibilities:

Perform yield/diagnostics analysis for PMIC products across different manufacturing stages (wafer sort, final test, etc.).

Identify and investigate yield loss mechanisms using statistical tools and electrical failure data.

Collaborate with foundries, test engineers, and process teams to drive root cause analysis and corrective actions.

Monitor yield trends and develop dashboards or reports to track key performance indicators.

Work new product introduction (NPI) by providing yield risk assessments and early-stage data analysis.

Work with BCD process technologies and HV device characteristics to interpret failure signatures and process sensitivities.

Develop yield models to forecast yield of future products for business assessment & supply planning.

Qualifications:

M.S. or Ph.D. in Electrical Engineering, Semiconductor Physics, or a related field.

Experience in yield/diagnostics analysis, data mining, or failure analysis in the semiconductor industry.

Familiarity with PMIC architecture and testing methodologies.

Proficiency in data analysis tools such as JMP, Excel, Power BI.

Strong problem-solving skills and ability to work in a cross-functional environment.

Good communication skills in both English and Mandarin.

Preferred Qualifications:

Strong knowledge of high-voltage devices such as LDMOS, with the ability to interpret and analyze device characteristics.

Familiarity with BCD process flow, PCM, and inline metrology.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

 

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