**Introduction** IBM Research takes responsibility for technology and its role in society. Working in IBM Research means you'll join a team who invent what's next in computing, always choosing the big, urgent and mind-bending work that endures and shapes generations. Our passion for discovery, and excitement for defining the future of tech, is what builds our strong culture around solving problems for clients and seeing the real world impact that you can make. IBM's product and technology landscape includes Research, Software, and Infrastructure. Entering this domain positions you at the heart of IBM, where growth and innovation thrive. **Your role and responsibilities** We are seeking a skilled and motivated PDK Automation Engineer to join our technology enablement team. This position plays a critical role in bridging semiconductor process development and physical design enablement by developing and maintaining Process Design Kits (PDKs), automation scripts, and design infrastructure. In this role you will work closely with design, integration, and development engineers to create robust design rule decks, parameterized cells (pcells), and automation flows that support efficient and accurate layout development using industry-standard EDA tools. You will be responsible for the following: * PDK Development: Develop, maintain, and distribute comprehensive Process Design Kits (PDKs) that accurately represent semiconductor technologies. * Design Rule Implementation: Implement and maintain DRC/LVS rule decks using industry-standard EDA tools such as Cadence Pegasus, Siemens Calibre, or Synopsys ICV. * Pcell Creation: Create, maintain, and support parameterized layout cells (pcells) using Cadence Skill and related scripting languages. * Automation Scripting: Develop automation scripts to streamline layout creation, verification, and design environment setup. * Technology Collaboration: Work closely with technology development teams to translate process parameters into physical design rules and design enablement features. * User Support & Documentation: Provide documentation and support for internal and external users of the PDK and design environment. * Design Compliance: Ensure developed layouts and design kits are compliant with foundry-specified DRC and LVS rules. * Continuous Improvement: Contribute to continuous improvement of the PDK infrastructure and layout automation frameworks. **Required technical and professional expertise** * Bachelor’s Degree in Computer Science, Computer Engineering, Electrical Engineering or related field with experience in VLSI chip development or semiconductor technology. * A minimum of 5+ years of experience in PDK development, semiconductor layout, or design enablement. * Coding proficiency with software or scripting languages (C, C++, Python, Perl, etc) for automation purposes, with 3+ years of experience. * Familiarity with layout verification tools from Cadence Pegasus, Synopsys ICV, or Siemens Calibre, including design rule checking (DRC) with 5+ years of relevant experience. * Proficiency with Cadence Virtuoso Layout tools and Cadence Skill languages. * Basic understanding of semiconductor process technology and layout ground rules. * Strong understanding of Linux environments and shell scripting with a minimum of 2+ years of experience. * Familiarity with physical semiconductor layout and technology ground rules. * Demonstrated communication and collaboration skills to work effectively in cross-functional teams. * Troubleshooting and problem-solving abilities in a collaborative environment. **Preferred technical and professional experience** * A minimum of 8+ years of experience in layout automation and design environment development. * Experience with advanced process nodes (10nm or below), including FinFETs and multi-patterning. * Strong knowledge of Front-End, Middle-End, and Back-End-Of-Line (FEOL, MEOL, BEOL) process components and layout practices. * Experience with version control systems such as Git and familiarity with collaborative software development workflows (e.g., GitHub, GitLab, or Bitbucket). * Experience in documenting and supporting PDK and design environment features for internal and external users. * Background in developing test structures and working with technology development teams. * Proven experience in developing automation solutions to enhance quality and runtime efficiency. * Extensive experience with Cadence Virtuoso layout tools and Cadence Skill language. IBM is committed to creating a diverse environment and is proud to be an equal-opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, gender, gender identity or expression, sexual orientation, national origin, caste, genetics, pregnancy, disability, neurodivergence, age, veteran status, or other characteristics. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status.