Owning block level PD activities
Work Experience
4 year experience in PD actvities,
Performing floor-planning and routing studies and implementation at block and full-chip level
Push down the top-level floorplan and clock to Partition.
IO Planning and bump planning
Closely working with Package team and reaching Die file milestones
Full chip and partition level timing analysis.
Evaluate low power techniques and power reduction opportunities
Perform clock distribution design and analysis
Perform Physical verification activities at full-chip level.
Drive technical activities of physical design during technology readiness, design & execution
In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience in Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes
Should have experience in handling >1M instance count, 1 GHz frequency designs
Should have experience in programming in Tcl/Tk/Perl to automate the design process and improve efficiency
Must have hands-on experience on PNR Suite from Cadence & Synopsys (Innovus & ICC2)
Strong experience in Static Timing Analysis (PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).