Job Requirements

Validate the structural and functional integrity of a complex 3D multi-die SoC integrating logic (FinFET) and compute-in-memory (FinFET/FDSOI/ULL/DRAM) dies using face-to-face and TSV-based stacking. This role will involve system-level package co-simulation, inter-die test coverage planning, and deep collaboration with foundries and OSATs to ensure robust thermal, mechanical, and electrical integrity. 

Perform cross-die and die-to-package interface verification using advanced 3DIC tools (Cadence 3D-IC, Synopsys 3DIC Compiler).Manage and align multi-PDK die abstraction models, IO ring integration, and DRC/LVS across die boundaries. Co-simulate package and die stack for parasitic-aware timing, leakage, IR drop, and signal integrity. Develop and implement pre-silicon testbenches to validate custom die-to-die interfaces and protocol correctness. Collaborate directly with foundry and OSAT technical teams to support TSV planning, microbump alignment, and die-to-die connectivity strategy. Lead package-level thermal and mechanical stress modeling, and actively drive thermal closure with iterative layout optimizations. 

Work Experience
7+ years of experience in SoC physical integration or packaging-aware verification for complex ASIC or multi-die systems. Proven expertise in 2.5D/3D SoC stack development including F2F and F2B bonding, TSV and microbump design. Hands-on experience integrating dies from multiple PDKs with dissimilar process nodes, voltage domains, and metal stacks.Strong understanding of multi-die thermal modeling, die attach thermal paths, and IR/conduction-aware layout. Demonstrated ability to interface with foundry and OSAT teams for technical bring-up, reliability, and stack planning. Tools: Cadence 3D-IC, Allegro Package Designer, ANSYS Thermal, Redhawk, Synopsys IC Compiler II, and Calibre 3D DRC/LVS