Lead Engineer
QuEST Global
Job Requirements
Experience level 4-10 years Experience with micro-architecture and design of digital IPs and subsystems Understanding the RTL design and Uarch of IPs and integrating them in sub-systems SoC IP Uarch definition and RTL development Own RTL Quality Checks: Clock Domain Crossing (CDC) check, Lint, etc. Design for Testability (DFT) checks Low Power Checks RTL Synthesis and STA support
Work Experience
Experience with micro-architecture and design of digital IPs and subsystems Understanding the RTL design and Uarch of IPs and integrating them in sub-systems SoC IP Uarch definition and RTL development Own RTL Quality Checks: Clock Domain Crossing (CDC) check, Lint, etc. Design for Testability (DFT) checks Low Power Checks RTL Synthesis and STA support
Experience level 4-10 years Experience with micro-architecture and design of digital IPs and subsystems Understanding the RTL design and Uarch of IPs and integrating them in sub-systems SoC IP Uarch definition and RTL development Own RTL Quality Checks: Clock Domain Crossing (CDC) check, Lint, etc. Design for Testability (DFT) checks Low Power Checks RTL Synthesis and STA support
Work Experience
Experience with micro-architecture and design of digital IPs and subsystems Understanding the RTL design and Uarch of IPs and integrating them in sub-systems SoC IP Uarch definition and RTL development Own RTL Quality Checks: Clock Domain Crossing (CDC) check, Lint, etc. Design for Testability (DFT) checks Low Power Checks RTL Synthesis and STA support
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