Minimum qualifications: + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. + 1 year of experience architecting networking ASICs from specification to production or equivalent practical experience. + Experience developing RTL for ASIC subsystems. + Experience in micro-architecture, design, verification, logic synthesis, and timing closure. Preferred qualifications: + Master's degree or PhD in Computer Science or a related technical field. + Experience in the following areas: performance debugging and optimization of complex workloads, design of performance tools, compiler design and code optimization, high-performance software development techniques, concurrent programming, or multi-core computer architectures. + Experience architecting networking switches, end points, and hardware offloads. + Excellent problem-solving and debugging skills. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. + Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more. + Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks. + Participate in synthesis, timing/power, and field-programmable gate array/silicon bring-up. + Participate in test plan and coverage analysis of the block and SOC-level verification. + Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.