Company:Qualcomm Semiconductor Limited

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Overview

This is a design position in the I/O Pad design team working on delivering quality low power I/O IP in state of art CMOS/FinFET/GAA technology nodes for Qualcomm's advanced mobile baseband, Auto, IOE/IOT & consumer products. Join QCT's IP team in designing and implementing I/Os for Qualcomm's next generation chipsets. The team is responsible for the complete design lifecycle, from system-level concept to tape out and post-silicon support, of advanced digital and mixed-signal ASIC designs in advanced CMOS/FinFET/GAA processes.
 

Responsibilities

Mixed-signal transistor level circuit design for General Purpose I/O (GPIO) and Custom I/Os, including specialty I/O such as eMMC, SDC, I2C, SLIMBus, RFFE, SPMI, Soundwire and multi-level voltage I/Os using low voltage transistors.Circuit design & Simulations for I/O circuitryWork with layout, packaging and system engineers to meet design specifications.Work closely with modeling & characterization team to provide front & back end models for their design.

The ideal candidate would possess the following qualifications

Proven track record of mixed-signal transistor level circuit design in the field of I/Os.Recent experience in I/O designs for wireless devices including Low-Power I/O design.Solid understanding of related CMOS, FinFET and GAA process technology issue.Familiar with I/O design methodology & flow, Calibration, JTAG design requirements, understanding of analog circuitry.Familiarity with ASIC flow: Synopsys libraries, LEF, CPF, UPF, Place & Route & understanding of top level verification flow.Familiar with Power & Signal Integrity and understanding of signal switching, noise & design issues.Experience in Cadence Virtuoso (Layout, Schematic, Simulation)Experience/skills in the following areas are highly valued: SKILL, PYTHON & TCL scripting, writing Verilog/VHDL, IBIS modeling, characterization and generating .LIBs.Familiarity with package/board constraints is a plusProven successful track record as a team player with an engineering team.Excellent communication skills and ability to work across multiple teams in multiple locations.Possess accountability and ownership.All levels of CMOS, FinFET & GAA IC development experience.

Educational Requirements

Required: Master's in Electrical or Computer Engineering

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.

 

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