Manage a team of 25 Verification engineers in low and high-speed controllers’ knowledge (+UVM)

Knowledge on High Speed Protocal PCI Express GEN1-GEN5

Experience in using VIPs of (PCI-Express

Should be good in System Verilog and UVM

Should have good knowledge in PCI-Express of Phy Layer; Data Link Layer and Application Layer

Knowledge Coverage and Assertions in System Verilog

Experience in Scriptin Languages Perl or Python

Debugging and Problem-Solving

Communication Skills

Team Collaboration

Project Ownership and Initiative