Job Requirements
BS, MS or equivalent degree with relevant courses in VLSI engineering,Scan insertion & ATPG using Fastscan/TestKompressPattern Simulation with and without timing annotation & debugging simulation mismatches (VCS/Modelsim/NCSim).Familiarity with WGL/STIL file formats.Scan compression techniques.Experience in Memory BIST insertion tools (preferably Tessent)Experience (Good understanding) in memory repair implementation.Boundary Scan, JTAG conceptsBasic understanding of Tester requirements, basics of synthesis and timing. Exposure to SoC level DFT.

Work Experience

Sr/Staff DFT Engineer shall be responsible and own all aspects of DFT which includes MBIST insertion, scan insertion, verification, pattern delivery and support test & product engineering teams.

Experience ranges from 6 to 10

Boundary Scan,  EDT/SCAN, SSN, IJTAG, LBIST, FBIST, ATPG, MBIST.