**Summary:** Manage an ASIC design verification team and/or managers responsible for various processing blocks in a SOC. Drive verification planning and execution, innovative verification methodology development, functional and code coverage closure. Participate in silicon architecture, micro-architecture development, interface with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams **Required Skills:** Design Verification Engineering Manager Responsibilities: 1. Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts 2. Contribute to and drive development of and maintain overall silicon strategy aligned to corporation's Long Range Plan objectives 3. Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing 4. Build, lead, and support a team of ASIC engineers through hiring, training, and guidance to drive on-time and on-budget product delivery 5. Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers 6. Support engineering teams to define, debug, implement and deliver total solutions around purpose built ASICs 7. Define, implement and maintain key performance indicators (KPI) for areas of responsibility 8. Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors 9. Support managers supporting design verification team **Minimum Qualifications:** Minimum Qualifications: 10. B.S. or M.S. degree in Computer Engineering or Electrical Engineering, relevant technical field, or equivalent practical experience 11. 12+ years experience in ASIC/SoC design verification 12. 8+ years of experience as a People Manager, leading people managers and senior ICs. 13. Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal 14. Track record of first-pass success in ASIC Development 15. Experience working across multiple projects and adjusting priorities in partnership with stakeholders 16. Experience managing and delivering UVM constrained random test benches 17. Experience with interpreting functional specs and creating comprehensive test plan 18. Experience managing managers who are supporting small/mid size teams **Preferred Qualifications:** Preferred Qualifications: 19. Hands-on experience with complex subsystems like memory, LPDDR, HBM, cache, PCIe, or network-on-chip including performance verification 20. In depth knowledge of at least one of these areas - video coding standards, signal processing algorithms, neural networks and machine learning concepts, and/or other neural network development framework 21. Experience in formal verification techniques and methodologies **Industry:** Internet