Design Engineering Director -HPP
The role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence.
Candidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical.
Minimum Qualifications & Professional Experience:
• 10-15 years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• 2-3 years of management experience leading/mentoring a small team of engineers
• Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/
• Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures.Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards reliability qualification & specificationExpert level knowledge in Verilog RTL coding for FPGA, python,C/C++
The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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