Design Engineer II
Cadence
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.BTech/ MTech in Engineering4+ years of VLSI industry experience in Verification.SOC level verification experience preferredIP or Subsystem or SOC level verification experienceShould be able to develop test plans, testsStrong knowledge of SV, UVM. Should be able to create verification environment using UVM methodologyShould be able to develop bus functional models, monitors, checkers and scoreboards.Should have experience in coverage driven verification closure.Strong individual contributor with good debug, problem solving skillsWorking knowledge of verification cycle for any complex IP/SOC for atleast one/more projects.We’re doing work that matters. Help us solve what others can’t.
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