Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
The Cadence Advantage
The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer successMultiple avenues of learning and development available for employees to explore as per their specific requirement and interestsYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.Job responsibilities:
BE/BTECH/ME/MTECH Or Equivalent Degree
Job Description
Sr. Design Verification engineer with strong high-speed interface experience ( UCIe ,PCIe, CXL, Ethernet, NVMe,).
2+ years DV experience. Strong with UVM and SV.
RESPONSIBILITIES:
Develop test plans, tests , and verification infrastructure for complex IP’s/sub-system/SOC’s.Create verification environment using UVM methodology.Create reusable bus functional models, monitors, checkers, and scoreboards.Drive functional coverage driven verification closure.Work with architects, designers and DFT teams.SKILL SETS:
BTech/ MTech with 2-7 years of experience. Or EquivalentIP/Sub-system/SOC level verification experience.Expert in developing test bench/test case using System Verilog & UVM.Experience with code coverage, functional coverage & assertions is desired.Experience in the following areas:UCIE or PCIEBus protocols (AXI/AHB/APB)Exposure to industry standard verification tools for simulation and debugGood debugging and problem-solving skills.Good communication skillsWe’re doing work that matters. Help us solve what others can’t.