Role Proficiency:

Ability to e xecute any small to mid size customer project in any field of VLSI Frontend Backend or Analog design with minimal supervision

Outcomes:

     Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.      Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time On time quality delivery approved by the project lead/manager

Measures of Outcomes:

     Quality –verified using relevant metrics by Lead/Manager      Timely delivery - verified using relevant metrics by Lead/Manager      Reduction in cycle time and cost using innovative approaches      Number of trainings attended      Number of new projects handled

Outputs Expected:

Quality of the deliverables:

Ensure clean delivery of the design and module in-terms of ease in integration at the top level Meet functional spec / design guidelines 100% of the time without any deviation or limitation Documentation of the tasks and work performed

Timely delivery:

Meeting project timelines as requested by the program manager Support the team lead in intermediate tasks delivery

Team Work:

Participation in team work; supporting team members/lead at the time of need Able to perform additional tasks in-case any team member(s) is not available

Innovation & Creativity:

Automate repeated tasks to save design cycle time as a necessary approach Participation in technical discussion
training
forum

Skill Examples:

     Languages and Programming skills:a.     System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one)      EDA Tools: a.     Cadence Synopsys Mentor tool sets (one or more)b.     Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one)      Technical Knowledge: (any one)a.     Partially implement IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb.     Strong in Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec.      Strong knowledge in Physical Design / Circuit Design / Analog Layout d.     Strong understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione.     Strong knowledge of Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design      Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below      Strong communication skills      Good analytical reasoning and problem-solving skills with attention to details      Able to deliver the tasks on-time per quality guidelines and GANTT in every instance.      Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present to a level needed to execute the project

Knowledge Examples:

     Frontend / Backend / Analog Design:a.     Project experience in any of the design by executing any one of – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.b.     Strong understanding of the design flow and methodologies used in designing      Understanding of the technical specs and assigned tasks: Understand the assigned tasks and have strong knowledge to execute the project tasks assigned by the client / manager as per shown skill

Additional Comments:

Memory Design Job description 1) Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF/3FF/2FF Technologies. 2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic. 3) Development of critical path and characterization flow to perform detailed margin and characterization simulations. 4) Statistical Analysis of Bit-Cell, Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off 5) Design Tuning/optimizations to meet target PPA, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets. 6) Logic simulations and detailed timing analysis of key paths in high speed memory design. 7) Good understanding and design experience of all the SRAM additional features and architecture options like low power features, redundancy features and pipeline features. 8) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design. Skill Sets 1) Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits 2) Experience in Designing and Driving one or many Memory Compilers Specifications to final release 3) Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing. 4) Complete hands on experience in using Cadence/Mentor schematic/layout editor tools 5) Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, Nanotime, ESPCV, nWave, waveform viewer etc 6) Experience in Skill/Perl/Python Scripting is a strong plus 7) Experience in Understanding the layout design issues in sub nanometer regime is a Plus