**Summary:** Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Formal Verification Engineer, you will be part of a team working with the best in the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Verification Engineer, Formal Responsibilities: 1. Provide technical leadership in Formal Verification 2. Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level 3. Work with Architecture and Design teams to come up with Formal Verification specification and implementation 4. Define Formal Verification scope, create Formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level 5. Build reusable/scalable environments for Formal Verification and deploying tools 6. Evaluate and recommend EDA solutions for Formal Verification 7. Provide training for internal teams and mentoring engineers related to Formal Verification Technology **Minimum Qualifications:** Minimum Qualifications: 8. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 9. 5+ years of experience in Formal Verification 10. Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc 11. Experience with Formal Verification methodologies, complexity reduction techniques and abstraction techniques 12. Experience using analytical skills to craft novel solutions to tackle industry-level complex designs 13. Demonstrated experience with effective collaboration with cross functional teams 14. Fluency in hardware description languages, such as SystemVerilog and SVA 15. Proficiency in scripting languages such as Python, Perl, or Tcl 16. Experience with JasperGold or VC-Formal **Preferred Qualifications:** Preferred Qualifications: 17. 8+ years of experience in Formal Verification 18. Experience to quickly understand and interpret specifications and extract design behaviors/properties 19. Experience in formal property verification of complex compute blocks like DSP, CPU, GPU or HW accelerators 20. Experience with complex SoCs 21. Formal verification experience in clock domain crossing, IP-XACT based register verification and low power 22. Experience with development of fully automated flows from specification to fully verified designs 23. Experience with simulators and waveform debugging tools **Industry:** Internet