Join the Silicon One Team at Cisco in Armenia, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work firsthand with the Physical Design of intricate chip partitions.
Your ImpactThis role offers a unique opportunity to make a significant impact at shaping the future of networking innovation within the Cisco Silicon One initiative. As a key technical leader, you will drive the development of next-generation silicon architecture, guiding your team in delivering solutions that power advanced global networks. If you are passionate about leading diverse technical domains and inspiring innovation, this position is for you. You will shape strategies, mentor leading engineers, and foster collaboration to accelerate the creation of industry-leading silicon solutions. Beyond technical leadership, you’ll be part of a team that is changing the world—working alongside visionary leaders and building positive relationships in a supportive environment where collaboration and collective success are prioritized.
Responsibilities: Participate and contribute to chip sensors architecture definition and discussions. Generate and verify different configurations of sensor to ASIC chip Implement testbenches, run simulation and verification Help define, evolve, and support sensor integration in block and chip level. Collaborate with physical design and front end teams close design timing and place-and-route issues Triage, debug, and root cause simulation, software bring-up, and customer failures. Minimum Qualifications: BS/MS in Electrical Engineering or Computer Science 10+ years of experience in ASIC design Excellent Verilog/System Verilog programming skills. Knowledge of Silicon Lifetime Managements IP, their usage, verification specs Experience with simulators/synthesis/static timing constraints and tools Preferred Qualifications: Good understanding of verification methodologies and flow Strong interactive and waveform debug skills. Excellent English verbal and written communication skills. Self-motivated, able to work independently or as a team player Experience in block level synthesis, place and route, timing closure is ideal. Scripting experience (Python, Perl, TCL, shell programming) highly valuable.#WeAreCisco
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