**Summary:** Meta is looking for an experienced ASIC Packaging Engineer, Signal Integrity, and Power Integrity focus for its ASIC packaging team to support the development of custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal for our ASIC roadmap. We are building a competency in Packaging technology to support the development of custom silicon and looking for expertise in hardware development and integration of machine learning clusters, both server and fabric with focus on the impact they can create as part of a world-class engineering team. **Required Skills:** ASIC Package Engineer Responsibilities: 1. Drive chip-package-system co-design by driving signal and power integrity requirements analysis and optimization to involved in the product definition and optimize chip floorplan, power tree structure, netlists, etc for High Performance Computing based on 2.5D/3D package technology 2. Hands on experience in interposer or fanout packages for both organic and inorganic interposer with or without bridges such as Cowos-L, cowos-R, EMIB, embedded fanout bridge from OSAT 3. Hands on experience of substrate development and trade off relative to SI/PI, mechanical, thermal and electrical analysis 4. Development of advanced packaging technologies (SMT, solder ball attach, and other assembly process) roadmap for AI/ML and networking products applications 5. Drive disruptive packaging technologies roadmap to create differentiation for Meta ASICs 6. Influence ASIC vendors, foundry and OSATs partners roadmap and align with Meta ASICs roadmap 7. Lead development of disruptive advanced packaging technologies from concept to product including Test vehicle definition and building with ecosystem partners 8. Drive ecosystem partners for 2.5D/3D and large packages SMT roadmap 9. Perform package design for AI/ML and networking applications custom Si with single-chip/multi-chip and SiP/module packaging, design feasibility studies and analyses to ensure good manufacturing at ODM 10. Participates early on Si/package/PCB/system co-design, and ODM SMT manufacturing work in product development design reviews providing feedback on manufacturability and helps incorporate latest technology advancements and design rules 11. Work with internal Si, architecture and system teams and externally engaged partners, ODM, design houses and OSAT companies 12. Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve package form factor for next generation versions of current products 13. Create, conduct, and analyze Design of Experiments (DOE) for development and sustaining activities 14. Work cross-functionally with design, NPI, quality and reliability, manufacturing teams and support new technology integration into products 15. Support selection, and qualification of external partners (ODM, OEM, OSAT) 16. Drafting of SMT assembly and advanced packaging technology definition documentation 17. Collaborate with internal and external stakeholders to ensure seamless integration of packaging technology into product development cycles 18. Stay abreast of the latest advancements in advanced packaging technologies and market trends 19. Identify and evaluate emerging technologies with potential for future applications 20. Ability to travel internationally, typically once per quarter **Minimum Qualifications:** Minimum Qualifications: 21. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 22. 10 years of experience in advanced packaging with surface mount technology and assembly process development and manufacturing 23. In-depth knowledge of flip chip, 2.5D and 3D packaging technologies 24. Experience taking products from concept to production including development of manufacturing specifications, vendor qualifications and improvement of manufacturing efficiencies and costs 25. Effective communication skills 26. Experience working effectively with cross-functional teams 27. Participate in silicon architecture/package/PCB/system co-design work collaborating with downstream system design teams and upstream silicon designers to develop holistically optimal solutions 28. Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors 29. Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve bandwidth, power efficiency and package form factor for next generation versions of current products 30. Lead package development to establish package manufacturability and reliability 31. Collaborate with multi-functional teams within Meta and define package requirements **Preferred Qualifications:** Preferred Qualifications: 32. Masters Degree or PhD in Materials Science, Mechanical Engineering, or other related disciplines 33. 15+ years of experience in advanced packaging assembly process, SMT 34. In-depth knowledge of 2.5D and 3D packaging technologies, including silicon interposers, TSVs, and microbumps 35. Proven understanding of fanout advanced packaging technologies 36. Experience working with ODM, assembly packaging, OSAT, and foundry partners 37. Proven technical understanding of full range of semiconductor packaging materials, material interactions, SMT processes, PCB design and layout tools, failure mechanisms and analytical techniques 38. Familiarity or experience with Finite Element Modeling (FEM) of thermal and thermo-mechanical behavior of packages 39. Proven knowledge of packaging industry standards (IPC, JEDEC, IEEE, ISO, ANSI) 40. Understanding of package qualification and reliability methods and failure analysis **Public Compensation:** $173,000/year to $249,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.