The Silicon One Team at Cisco is seeking an ASIC Engineering Technical Leader to join our team in Armenia. In this role, you will be responsible for defining Physical Design methodologies and developing automated flows for advanced technology nodes. You’ll also have the opportunity to work on the Physical Design of complex chip partitions, leveraging ground breaking tools and techniques.
Your primary focus will be on enhancing Physical Design flows and methodologies. This includes developing automation for the flows, optimizing processes, and, when needed, contributing directly to the Physical Design work itself. You’ll also work closely with EDA tool vendors to ensure seamless integration and support. The ultimate goal is to refine and simplify Physical Design flows, making them more efficient and user-friendly for other teams.
At Cisco, our team culture is built on support, alignment, and collaboration. We take pride in fostering a cohesive, team-oriented environment where every member contributes to our shared success.
Your ImpactApply a deep understanding of physical design flows to develop, maintain, and optimize efficient design processes.Perform gate-level netlist synthesis to accurately translate design specifications into functional digital circuits.Oversee the physical implementation process, with a focus on automating workflows for floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (PV), ensuring optimal chip layouts.Conduct static timing analysis to meet timing constraints and support successful design validation and signoff closure.Develop utilities and dashboards to enhance flow integration and improve usability.Minimum Qualifications: 7+ years of experience in Physical Design, preferably with involvement in the full cycle from RTL to GDS.Strong scripting skills in Python, Perl, TCL, and shell programming.Expertise in block-level synthesis and Place-and-Route (PnR).Proficiency in flow automation.Excellent verbal and written communication skills in English.Preferred Qualifications: Experience with Static Timing Analysis (STA) and timing closure.Familiarity with Silicon Lifetime Management IP, including its usage and verification specifications.Proficiency in Verilog/System Verilog programming.Solid understanding of verification methodologies and workflows.Self-motivated, with the ability to work independently or collaboratively as part of a team.#WeAreCisco#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.
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