Description Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in the application of new technologies to large scale server deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve your products performance, quality and cost. We’re changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today. Key job responsibilities Key job responsibilities • Develop, implement and verify state-of-the-art Design for Test (DFT) architectures • Work with block designers to integrate DFT implementations • Work with physical design team to setup and implement DFT insertion flow • Develop high coverage and cost effective DFT methodologies • Perform RTL coding and Verification • Participate in Silicon debug and write scripts to effectively handle ATE related data • Communicate and work with team members across multiple disciplines Basic Qualifications BS degree or higher in EE, CE, or CS with a graduation date between December 2022 and October 2025 Academic, internship, or professional experience with VLSI design or DFT Familiarity with automation script development and/or software development Preferred Qualifications MS degree in EE, CE or CS Project/internship experience with DFT (SCAN, JTAG or MBIST) Good breadth of knowledge in chip design concepts from micro-architecture through physical design Experience in programming and scripting with Perl, Python or Tcl Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.