Minimum qualifications: + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. + 5 years of experience with two or more of the following: CPU, GPU, ISP, display, video codecs, memory controllers, fabrics, compression, storage, OTP, interrupts, interfaces, debugging/profiling mechanism, power management system. Preferred qualifications: + Master’s degree or PhD in Computer Science, Electrical Engineering, or a related field. + Experience designing/implementing or validating RTL for CPU, GPU, Fabric, Memory, Caches, Camera, Video, Display, and Access Control elements. + Experience analyzing multi-IP workload usecases, tools, and simulators at different abstraction levels (Cycle Accurate, TLM, or Functional). + Experience with a scripting language. + Knowledge of hardware performance monitors or profiling, power management, and optimization. + Knowledge of OS, Firmware, Software Stack, OpenGL, OpenCL, Java, Codec. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will collaborate with software and hardware architects to explore ASIC design trade-offs. You will develop and use analytical tools, simulation, emulation, and post-silicon measurements to perform holistic analysis of large complex ASIC designs. You will participate in the development of technology in compute, media, fabric, memory, etc., and filing associated patents. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) . + Participate in architectural design and evaluation of future ASIC designs. + Participate in creating architectural specifications for ASIC. + Optimize top-level architectural definition to handle complex multi-IP flows. + Communicate the analysis results in both qualitative and quantitative fashion. + Develop modeling simulators and architectural models of various subsystems within an ASIC to evaluate interactive and novel workloads. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.